1. Field of the Invention
The present invention relates to vertical MOS power transistors and more specifically to the protection of a vertical MOS power transistor coupled with a vertical MOS current measurement transistor.
2. Discussion of the Related Art
A vertical MOS power transistor is generally formed of a large number of identical elementary cells in parallel. To measure the current in this transistor, it is usual to associate therewith a measurement transistor formed of a smaller number of the same elementary cells, submitted to the same biasing conditions. When the load of the power transistor is an inductive load, a negative voltage appears across the load upon turning-off of the power transistor. This voltage is likely to trigger the conduction of parasitic elements and to damage the power transistor.
FIG. 1 shows a circuit including a vertical MOS power transistor T1 formed of n elementary cells T11 to T1n, associated with a vertical MOS measurement transistor T2 including m elementary cells T21 to T2m, with m being much smaller than n. The drains D of the elementary cells of the power transistor and of the measurement transistor are connected together to a high potential Vcc. The gates G of the elementary cells of the power transistor and of the measurement transistor are connected together to a control terminal G. The sources S1 of the elementary cells of the power transistors are interconnected and connected by an inductive load L to the ground. The sources S2 of the elementary cells of the measurement transistor are interconnected and connected to a current source I.sub.ref. The voltage difference between terminals S1 and S2 gives an indication of the fact that the current in the power transistor is greater than or smaller than a threshold equal to (n/m)I.sub.ref.
It should be noted that in certain applications, current source Iref may be replaced with a resistor R, when the circuit is to measure a charge resistance instead of a charge current.
FIG. 2 schematically shows a vertical cross-sectional view of a portion of a silicon wafer 2 in which are made transistors T1 and T2. The drain of an elementary cell corresponds to substrate 21 of the wafer. Area 21 is connected via a heavily-doped N-type (N.sup.+) area 20 to a metallization 22 connected to drain terminal D of the circuit of FIG. 1.
The source of an elementary cell corresponds to an N.sup.+ -type ring 25 formed in a P-type well 23. Well 23 generally comprises a heavily-doped P-type (P.sup.+) central area 24. A source metallization 26 is in contact with the central portion of each well 23 and with ring 25.
The gate of an elementary cell is formed by a polysilicon layer 27, isolated from the wafer surface by a dielectric, which covers a channel area included between the external periphery of ring 25 and the external periphery of well 23. Gates 27 are interconnected to a gate node G.
FIG. 2 shows three elementary cells of power transistor T1. Metallizations 26 of these elementary cells are connected to a same source node S1. Similarly, two elementary cells of measurement transistor T2 have been shown, metallizations 26 of these cells being connected to the same source node S2.
FIG. 3 shows at a greater scale a portion of FIG. 2 on which parasitic elements existing between two adjacent elementary cells have been shown. Conventionally, gate 27 also covers the area of substrate 21 included between the two elementary cells. This metallization, isolated from substrate 21, corresponds to a gate of a parasitic transistor T3 of PMOS type formed of a P-type well 23 of a first elementary cell, of an N-type substrate portion 21, and of a second P-type well 33 of a second elementary cell.
On the other hand, the association of an N.sup.+ -type area 25, of a P-type well 23, and of lightly-doped N-type substrate 21, forms an NPN-type bipolar parasitic transistor, the emitter of which is area 25, the collector of which is area 21, and the base of which is well 23.
Consider an elementary cell T1i of the power transistor adjacent to an elementary cell T2j of the measurement transistor, the sources of which are respectively S1 and S2. An NPN-type bipolar transistor T4 is connected between source S1 and drain D of the cell of transistor T1. The base of transistor T4 is connected to the drain of a parasitic PMOS transistor T3. Similarly, an NPN-type bipolar transistor T5 is connected between source S2 and drain D of the cell of transistor T2, the base of transistor T5 is connected to the source of MOS transistor T3. MOS transistor T3 is controlled by gate G common to transistors T1 and T2.
As illustrated in FIG. 1, if load L of transistor T1 is an inductive load, the voltage across the load, that is, on source S1, will become negative when the power transistor will be off. Gate G, which corresponds to the gate of transistor T3 is then negative but at a voltage greater than source S1, and source S2 is at a potential close to the ground. If the voltage is very negative on source S1, MOS transistor T3 which is then on lets through a high current between terminals S2 and S1. When this current, which flows, in particular, under N.sup.+ region 25, exceeds given threshold, bipolar transistor T4 turns on. This creates a short-circuit between source terminal 26 and drain terminal 22 of cell T2i. Terminal 26 being at a very negative potential and terminal 22 being at potential Vcc, a destructive breakdown of the structure may result therefrom. The current which flows through transistor T4 depends on the gain of this transistor. Now, in the framework of modem technologies, the size of wells 23 decreases and the doping level of areas 24 is reduced. As a result, the gain of parasitic bipolar transistors T4 increases and thus the destructive breakdown risk increases.
The present inventors have thus searched various ways for eliminating the destructive effects linked to the turning-on of parasitic bipolar transistors by the above-mentioned parasitic MOS transistors.
FIG. 4 very schematically shows a top view of a device such as shown in FIG. 1. Block T1 represents the surface occupied by the elementary cells of power transistor T1 and block T2 represents the surface occupied by the elementary cells of measurement transistor T2. T3 symbolizes the parasitic MOS transistors existing between the adjacent cells of the power transistor and of the measurement transistor.
FIG. 5 shows a vertical cross-sectional view of a first solution to avoid the above-mentioned destructive breakdowns. The structure is very close to the structure shown in FIG. 2, and the same reference characters designate the same elements. Between two adjacent elementary cells T1i and T2j, respectively belonging to the power transistor and to the measurement transistor, is interposed a buffer cell B. Such a buffer cell may be implemented by eliminating the N.sup.+ implantation of the sources in an elementary cell of T1. There no longer exist parasitic bipolar transistors.
FIG. 6 very schematically shows a top view of a device such as that in FIG. 5. Block T1 shows the surface occupied by the elementary cells of power transistor T1, block T2 represents the surface occupied by the elementary cells of measurement transistor T2, and block B represents the surface occupied by the buffer cells placed between the power transistor and the measurement transistor. Transistor T3 represents the parasitic MOS transistors existing between the elementary cells of measurement transistor T2 and the adjacent buffer cells B.
In FIG. 5, the currents flowing in normal operation from the source of elementary cells of the power and measurement transistors have been represented by arrows. The elementary cells adjacent to buffer cells B receive, in normal operation, a greater current density than the other elementary cells. The ratio between the currents flowing through transistors T1 and T2 varies with the value of the currents. This imbalance of the currents no longer enables simply determining the current in power transistor T1 based on the current flowing through measurement transistor T2.